MODELING AND SIMULATION OF FinFET SRAM FOR NANOSCALE DEVICES
نویسنده
چکیده
Sub-threshold leakage and process-induced variations in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control Vt and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. In this work, low power and robust 6T SRAM cell using FinFET has been proposed. When SRAM is in idle mode, leakage power is reduced by the cells which are based on the Vt-control of the cross-coupled inverters of the SRAM cell. This scheme also results in increased Static Noise Margin (SNM) and low standby power consumption. HSPICE simulations for 32 nm FinFET technology is used for analyzing the efficiency. The results show considerable improvements in terms of the standby power as well as read SNM. Keywords-FinFET, SRAM, low power, design, double gate devices
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